PIC MICROCONTROLLER

PIC is a family of Harvard architecture microcontrollers made by Microchip Technology, derived from the PIC1640[1] originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to "Peripheral Interface Controller".[2][3]
PICs are popular with both industrial developers and hobbyists alike due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, and serial programming (and re-programming with flash memory) capability.
Microchip announced on February 2008 the shipment of its six billionth PIC processor.[4

The PIC architecture is distinctively minimalist. It is characterized by the following features:
Separate code and data spaces (Harvard architecture)
A small number of fixed length instructions
Most instructions are single cycle execution (4 clock cycles), with single delay cycles upon branches and skips
A single accumulator (W), the use of which (as source operand) is implied (i.e. is not encoded in the opcode)
All RAM locations function as registers as both source and/or destination of math and other functions.[2]
A hardware stack for storing return addresses
A fairly small amount of addressable data space (typically 256 bytes), extended through banking
Data space mapped CPU, port, and peripheral registers
The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).
Unlike most other CPUs, there is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.

PERFORMANCE:
Many of these architectural decisions are directed at the maximization of top-end speed, or more precisely of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs, and is still among the simplest and cheapest. The Harvard architecture—in which instructions and data come from conveniently separate sources—simplifies timing and microcircuit design greatly, and this pays benefits in areas like clock speed, price, and power consumption.
The PIC is particularly suited to implementation of fast lookup tables in the program space. Such lookups are O(1) and can complete via a single instruction taking two instruction cycles. Basically any function can be modelled in this way. Such optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 x 14-bit words on the 16F690) and by the design of the instruction set, which allows for embedded constants.
The simplicity of the PIC, and its scalar nature, also serve to greatly simplify the construction of real-time code. It is typically possible to multiply the line count of a PIC assembler listing by the instruction cycle time to determine execution time. (This is true because skip-based instructions take 2 cycles whether the skip occurs or doesn't.) On other CPUs (even the Atmel, with its MUL instruction), such quick methods are just not possible. In low-level development, precise timing is often critical to the success of the application, and the real-time features of the PIC can save crucial engineering time.
A similarly useful and unique property of PICs is that their interrupt latency is constant (it's also low: 3 instruction cycles). The delay is constant even though instructions can take one or two instruction cycles: a dead cycle is optionally inserted into the interrupt response sequence to make this true. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized.
The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. Other microcontrollers can do this in some cases, but it's awkward. The non-interrupt code has to anticipate the interrupt and enter into a sleep state before it arrives. On PICs, there is no need for this.
The three-cycle latency is increased in practice because the PIC does not store its registers when entering the interrupt routine. Typically, 4 instructions are needed to store the W-register, the status register and switch to a specific bank before starting the actual interrupt processing.